Many data processing systems are designed with subsystems that operate at different clock frequencies. This strategy can increase overall processing throughput by increasing the operating speed of select subsystems relative to the remaining subsystems. Typically, the performance of these faster subsystems is either critical to the overall performance of the system or relatively inexpensive to increase. One example of this design strategy is a data processing system with a single VLSI (very large scale integrated) data processor operating at a clock frequency some multiple times the clock frequency of an associated bus. In this case, all other subsystems in the data processing system operate at the lower bus clock speed. Generally, the ratio of the two clock frequencies may be expressed as the ratio of two integers: 2:1, 3:2, 4:1, etc. The range of these ratios reflects the pragmatic requirement that the two clock signals have some frequent phase alignment in which to synchronize inter-system communications. The more frequent the phase alignment, the greater the number of opportunities to transfer data between the fast data processor and the slower bus.
Data processing systems that have a data processor operating at a different clock frequency than an associated bus must synchronize data transfer between the data processor and the bus. For instance, in a 2:1 processor-bus system, it may be the case that the data processor does not assert an output signal during the correct phase of the bus signal if the data processor only asserts the signal for one processor clock cycle. Conversely, the bus will assert an input signal to the data processor for two processor clock cycles. Both of these scenarios result in unreliable data transfers. In the first case, data may not be transferred from the data processor to the bus at all. In the second case, the bus will transfer the same data twice to the data processor.
Known synchronization methods have limitations. In general, data transfer methods may be described as asynchronous or synchronous. Each of these methods has a different synchronizing problem.
In the asynchronous case, there are no timing requirements between two communicating subsystems other than minimum signal hold times. In one known solution, a slow output signal is sampled by a fast input device through a series of sequential latching elements. The clocking signal of the faster input device clocks each of the latching elements. Each successive latching element reduces the probability that a metastable state will be passed from the slower device to the faster device. Unfortunately, each additional latch increases the propagation time from subsystem to subsystem by an additional fast clock cycle.
In the synchronous case, there are timing requirements between the two communicating subsystems. In particular, a signal must be asserted during a particular phase of the clock signal of the receiving device. In a second known solution, a single latching element-multiplexer circuit links two subsystems operating at different clock frequencies. The latching element samples the output of the multiplexer coincident with each fast clock cycle. The multiplexer outputs either a previously latched value or an input signal. The output of the multiplexer is selected by a control signal such that it passes each input signal according to the timing constraints of the receiving subsystem. This solution is suitable only where the ratio of the two clock frequencies is an integer. In addition, a particular solution is typically only valid for one processor to bus clock ratio.